Intel® CoFluent™ Solutions
Models for Virtual Platforms/Prototypes
Virtual platform environments provide an efficient solution for creating SystemC-based virtual hardware platforms for embedded software development with fast instruction set simulators (ISS). Virtual prototypes are HW/SW co-verification environments. Creation of a TLM virtual platform or cycle-accurate virtual prototype relies on the assembly of models of standard IP blocks available in library. Proprietary or third-party IP that can't be found in a vendor's library have to be modeled by the user or a subcontractor. This can be a time-consuming and expensive task and can jeopardize virtual platforms' early software development time-to-market advantage.
Intel® CoFluent™ Studio offers an alternative to the manual modeling of IP and IP-level or platform-level test cases for virtual platforms/prototypes by providing an efficient graphical modeling entry and automatic SystemC TLM or Simics DML code generation. It offers up to 5x productivity gains compared to hand-programming and can be used by non-SystemC and non-DML experts. It accelerates the availability of a complete virtual platform environment and facilitates the creation of application-realistic workload use cases when software is not available yet.
Graphical models are captured and behaviors and timings are validated within Intel CoFluent Studio at a functional level. TLM SystemC or Simics DML code is automatically generated from the graphical description and can be integrated to SystemC-based virtual platform/prototype environments through the Accellera standard TLM-2.0 interface, or to the Simics environment through a DML interface.
Models can serve as executable specifications for implementation, offering a continuous development flow from executable specifications to virtual platforms.
Auto generate models
Intel® CoFluent™ Studio allows creation and automatic generation of SystemC and Simics models for:
- Any Accellera SystemC 2.2-based simulation environment
- Third-party simulation environment from Cadence, Mentor Graphics and Synopsys
Automatic SystemC TLM code generation allows reuse of IP or use case models for integration and simulation into SystemC-based virtual platform or virtual prototype environments.
When modeling hardware IP, the generated SystemC test case can be used as testbench for validating the RTL implementation.