Intel® CoFluent™ Solutions
Multicore Performance Analysis
Increasingly complex systems and new technologies are difficult to handle without computer-aided modeling and simulations giving a dynamic view on systems. System architects deal with two distinct but complementary parts, hardware and software, usually developed by two separate teams. As architects pass on work to engineers who develop the system, the probability for designers to deviate from the original vision is high. Explicit executable specifications that can be easily shared and analyzed, with test cases that can be reused to validate the design, ensures correct implementation of the design intent.
Intel® CoFluent™ Studio for System Architecting addresses advanced architectural design challenges by providing a higher abstraction level and offering a systematic modeling process. Our system-level design (SLD) encompasses a top-down approach that facilitates problems resolution by breaking-out complexity, and message-level modeling where complexity is easier to dominate. Intel CoFluent Studio abstracts multithreading, communications, and synchronization problems into intuitive graphical notations inspired from generic concepts found in real-time operating systems (tasks, events, message queues).
The description of multiprocessing execution platforms is achieved through generic models of processor, scheduler, bus, and memory. A rich set of scheduling and arbitration policies and customizable performance parameters provides full flexibility and independence in architecture exploration. The analysis of the real-time application execution on a multicore platform allows observing, understanding and optimizing macroscopic architectural dimensions such as task scheduling, bus transactions, memory footprint, resource load, power consumption, and performance estimation.
Value Proposition: Improving productivity, reducing risks and optimizing end-product.
- Simplifying multicore application decomposition: Processes and inter-process communications and synchronization.
- Graphical model = implementation blueprint: guiding embedded designers and providing execution time budgets for algorithms development.
- Avoid potential real-time problems ahead-of-time: before HW and SW availability, deadlocks, race conditions, and CPU starvation.
- Reduce project cancellations and delays
- Flexible architecture exploration free of limitations. Finding optimal architecture for parallel execution.
- Tasks allocation, CPU loads, and communications topology. Trade-off between performance and other requirements: Memory footprint, power, and cost.