Optimize 32nm SoC Platform Technology, 2nd Generation High-k/Met

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Optimize 32nm SoC Platform Technology, 2nd Generation High-k/Met

A 32-nm SoC Platform Technology with 2nd Generation High-k/Metal Gate Transistors Optimized for Ultra Low Power, High Performance, and High Density Product Applications

Abstract: A leading-edge 32-nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space.

This technology has been developed to be modular, offering mix-and-match transistors, interconnects, RF/analog passive elements, embedded memory, and noise mitigation options. The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently. Embedded memories include high density (0.148 um2) and low voltage (0.171 um2) SRAMs as well as secure OTP fuses. Analog/RF SoC features include high precision and high quality passives (resistors, capacitors and inductors) and deep-nwell noise isolation. Introduction As Moore’s Law continues to guide CMOS scaling down to the 32-nm node, SoC (System-on-Chip) integration of numerous functional circuit blocks has become the mainstream IC manufacturing trend.

However, new challenges to accommodate diverse requirements from integrating different system components constantly arise. Examples include high performance cores, low standby power always-on circuitry, high voltage I/O, high frequency RF, and precision analog circuits. This paper reports on a leading edge 32-nm high-k/metal gate SoC technology with a mix-and-match triple transistor architecture that enables independent optimization of transistor characteristics to meet the needs of different SoC circuit blocks.

Read the full Optimize 32nm SoC Platform Technology, 2nd Generation High-k/Met Paper.